In producing IC chips, generally a plurality of chip regions formed in a matrix state on a semiconductor wafer are partitioned, and an electronic circuit for an IC for each chip region is formed collectively. In the semiconductor wafer with these plural IC circuits built in, the chip regions are finally divided along scribe lines, thereby being separated into multiple IC chips. The semiconductor wafer with such IC circuits incorporated into is subjected to an electric test prior to dividing into respective chips by use of a probe assembly as disclosed, for example, in “Patent Document 1” cited below.
This probe assembly comprises a probe unit supported on a support table. Each probe of the probe unit has an inclined arm portion. Each inclined arm portion is extended from the support table obliquely downward toward the semiconductor wafer held by a vacuum chuck. An extended end, that is, the front end of each inclined arm portion is provided with a tip capable of contacting a corresponding electrode formed in each chip region of the semiconductor wafer. When the tip of each probe of the probe assembly is pressed toward the corresponding electrode, the tip of each probe is surely pressed against the corresponding electrode by taking advantage of flexural deformation of each inclined arm. By this pressing against the electrode, each electrode is connected to a tester body through the corresponding probe for an electrical test.
According to the probe assembly of the above-mentioned Patent Document 1, the arms are aligned to be inclined in one direction as well as in the other direction opposite to it according to the alignment of the corresponding electrodes. Because of this, with the flexural deformation of each inclined arm, a biasing force acts on the semiconductor wafer. However, as long as the IC circuit formed in each chip region is, for example, an IC circuit such as memories in which the same number of electrodes are aligned on both side portions of the chip regions symmetrically, in the probes the arm portions arranged in the opposite directions to each other are symmetrically arranged in correspondence to the each electrode row. The biasing forces due to the flexural deformation of these arms are balanced and set off, so that the biasing forces do not displace on the vacuum chuck the semiconductor wafer held on a vacuum chuck.
Consequently, according to the conventional probe assembly having such a symmetrical pattern in a probe arrangement, no lateral displacement parallel to the face of the vacuum chuck occurs at each test, thereby dispensing with fine adjustment following the displacement and thereby enabling a proper electrical test of each IC circuit formed on the semiconductor wafer.
Patent Document 1: Japanese Patent Appln. Public Disclosure No. 10-282147.